Semiconductor device and method manufacuring the same

ABSTRACT

A semiconductor device according to this invention comprises a substrate  100  in which semiconductor elements are formed, a first conductor  301  at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer  203  covering at least a portion of the first conductor  301 . The first insulative diffusion barrier layer  203  is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO) n SiH 4−n  (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

TECHNICAL FIELD

[0001] This invention relates to a semiconductor device having copperwiring of high reliability and method of manufacturing the same.

BACKGROUND ART

[0002] Heretofore, as wiring materials for LSI (Large Scaled IntegratedCircuits), aluminum or an aluminum alloy has been used predominantly.However, since aluminum has a low melting point (660° C.) and is poor inmigration resistance, it is difficult to cope with a higher integrationdegree and higher operation speed of LSI.

[0003] On the contrary, since copper has a melting point of 1083° C.which is higher than the melting point of aluminum and also has lowelectric resistivity (about ⅔ of aluminum as a bulk value), it isexpected as LSI wiring materials for the next generation. However,implementation of copper wiring has several subjects and one of them isan improvement in the reliability of wiring insulative films. It hasbeen known that copper diffuses easily into a dielectric film to lowerthe reliability (dielectric breakdown voltage) of an insulative film. Amethod of overcoming the problem has been disclosed in Japanese PatentLaid-open No. Sho 63-76455. In this method, diffusion of copper isprevented by disposing a metal layer as a diffusion barrier on theperiphery of copper wiring. However, this method requires steps offorming a metal film as a diffusion barrier layer over the entire uppersurface of copper wiring and then removing the metal film of unnecessaryportions in order to prevent a short circuit between adjacent wiring.When the distance between the adjacent copper wiring is narrowed, forexample, to 0.25 μm or less, it is difficult to remove the unnecessarymetal film between the wiring with good accuracy but no considerationhas been taken therefor.

[0004] The technique as the countermeasure is described in Proceedingsof VLSI Multilevel Interconnection Conference, 1993, pp 15. This is amethod of covering the upper surface of copper wiring buried in aninsulative film with a silicon nitride film as a diffusion barrierlayer. Since the silicon nitride film is insulative, there is norequirement for the step of removing the silicon nitride film formedbetween adjacent copper wiring. In addition, there is no worry of ashort circuit between the wiring even when the distance between thecopper wiring is narrowed. However, since the specific dielectricconstant of the silicon nitride film is as high as about 8 compared withthe dielectric constant of general dielectric films (about 4) used inLSI wiring steps, a parasitic capacitance between the adjacent wiring isincreased and the propagation speed of electric signals is lowered, butno consideration has been taken therefor.

[0005] The technique as the countermeasure is introduced in Proceedingsof the 1999 International Interconnect Technology Conference, 1999, pp109. This is a method of using a BLOk film (BLOk is the trade name ofproducts manufactured by Applied Materials, Inc.) comprising siliconcarbide as a main ingredient by using a plasma CVD as a diffusionbarrier layer for copper. Since the BLOk film is insulative like thesilicon nitride layer, it is not necessary for the step of removing theBLOk film formed between adjacent copper wiring. Further, since thespecific dielectric constant of the BLOk film is about 5, an increase inthe parasitic capacitance between the adjacent wiring can further bedecreased compared with silicon nitride.

[0006] Further, another technique as the countermeasure against theincrease in the parasitic capacitance between the wiring that is causedwhen the silicon nitride film is used as the diffusion barrier layer forcopper is introduced in Applied Surface Science, Vol. 91 (1995) pp303-307, and IEEE Electron Device Letters, Vol. 17, No. 12 (1996) pp549-551. They comprise a method of using an insulative film comprisingoxygen, nitrogen and silicon (hereinafter referred to simply as an SiONfilm) as the diffusion barrier layer for copper. Since the SiON film isalso insulative like the silicon nitride layer, it is not necessary forthe step of removing the SiON film formed between adjacent copperwiring. Further, since the leak current of the SiON film is relativelyapproximate to that of the silicon oxide film formed by the usualmanufacturing method, there is less worry that the leak currentincreases between the copper wiring to lower the LSI performance.Further, since the specific dielectric constant of the SiON film isabout 5.1 to 5.6, an increase in the parasitic capacitance between theadjacent wiring can further be reduced compared with silicon nitride.

[0007] Then, a description is made of another problem that occurs when asilicon nitride film is used as the diffusion barrier layer. In a casewhere a plurality of layers of copper wiring are integrated on oneidentical LSI, to establish electrical conduction between differentwiring layers, it is necessary to bore a via hole in the insulative filmbetween the wiring layers and bury the hole with a conductor. For thispurpose, it is necessary to make an opening in the silicon nitride filmas the diffusion barrier layer formed on the upper surface of the copperwiring. However, since the etching rate of the silicon nitride film islower than that of general insulative films, two major problems arise. Afirst problem arises in some cases where alignment error is presentbetween the copper wiring and the via hole made thereon. In a case wherethe via hole has an opening also in a region other than the copperwiring, if the silicon nitride film formed on the copper wiring isetched excessively, since the etching rate of the inter-wire insulativefilm below the silicon nitride film is high, the interlayer insulativefilm is engraved. If such phenomenon should occur, burying may sometimesbe insufficient upon burying the via hole with the conductor therebycausing conduction failure, or the insulative film of low dielectricconstant, when used for the inter-wire insulative film, is denatured topossibly deteriorate the wiring performance. A second problem ariseswhen the thickness of the fabrication mask for the via hole isinsufficient upon making the via hole on the copper wiring. When thesilicon nitride film on the copper wiring is etched upon making the viahole, the fabrication mask is etched simultaneously. In this case, whenthe thickness of the fabrication mask is insufficient, the interlayerinsulative film below the fabrication mask is etched possibly making thewiring resistance not uniform or the insulative film of low dielectricconstant when used below the fabrication mask is denatured todeteriorate the wiring reliability.

DISCLOSURE OF THE INVENTION

[0008] In the prior art using the BLOk film described above, noconsideration has been taken that the LSI performance is lowered due tolong time use since the diffusion preventive performance of the BLOkfilm against copper is poor compared with the silicon nitride film.Further no consideration has been taken that the current leakage mayoccur between adjacent copper wiring to deteriorate the LSI performancesince the BLOk film results in large leak current.

[0009] In the prior art using the SiON film, since the SiON filmcontains 15 to 33 atm % of nitrogen, the specific dielectric constant isgreater than 5. Therefore, this causes a problem that the parasiticcapacitance between adjacent copper wiring is increased to increase thewiring delay time, thereby deteriorating the LSI performance.

[0010] In the prior art using the BLOk film and the SiON film, whilemisalignment is caused between the copper wiring and the via hole or thereliability is lowered when the thickness of the fabrication mask isinsufficient, no concrete dissolution for the problems have beendisclosed.

[0011] A first object of this invention is to provide a semiconductordevice having copper wiring of high reliability and with less wiringdelay time.

[0012] A second object of this invention is to provide a method ofmanufacturing a semiconductor device of high reliability and havingcopper wiring with less wiring delay time.

[0013] The foregoing first object can be attained according to asemiconductor device of this invention comprising a substrate in whichsemiconductor elements are formed, metal wiring for interconnectingsemiconductor elements, and an insulative diffusion barrier layer forcovering at least a portion of the metal wiring, in which at least aportion of the surface on the periphery of the metal wiring has a regionmade of a material comprising copper as a main ingredient, a portion ofthe region made of the material comprising copper as the main ingredientis in contact with the insulative diffusion barrier layer, and theinsulative diffusion barrier layer has characteristics that a specificdielectric constant is 5 or less, a leak current of the insulativediffusion barrier layer at a test temperature of 140° C., under anelectric field strength of 2 MV/cm is 10 nA or less per 1 cm², and thedielectric breakdown lifetime of the insulative diffusion barrier layerwhen copper is used as an anode at a temperature of 140° C. is at least100 years.

[0014] The foregoing first object can be attained by a semiconductordevice according to this invention comprising a substrate in whichsemiconductor elements are formed, metal wiring for interconnecting thesemiconductor elements and an insulative diffusion barrier layer forcovering at least a portion of the metal wiring, in which at least aportion of the surface on the periphery of the metal wiring has a regionmade of a material comprising copper as a main ingredient, a portion ofthe region made of a material comprising copper as the main ingredientis in contact with the insulative diffusion barrier layer, and theinsulative diffusion barrier layer is formed by using a gas mixturecontaining at least an alkoxy silane represented by the general formula(RO)_(n)SiH_(4−n) (where n is an integer in a range from 1 to 3 and Rrepresents an alkyl group, aryl group or a derivative thereof) and anoxidative gas, by a plasma CVD method.

[0015] Further, the foregoing first object can be attained by asemiconductor device according to this invention comprising a substratein which semiconductor elements are formed, metal wiring forinterconnecting the semiconductor elements and an insulative diffusionbarrier layer for covering at least a portion of the metal wiring, inwhich at least a portion of the surface on the periphery of the metalwiring has a region made of a material comprising copper as a mainingredient, a portion of the region made of the material comprisingcopper as the main ingredient is in contact with the insulativediffusion barrier layer, and the insulative diffusion barrier layer isformed by using an inorganic silane gas or an organic silane gas and, anitrogen oxide gas or a gas mixture containing an oxygen atom-containinggas and a nitrogen atom-containing gas by a plasmas CVD method, andcomprises oxygen, silicon and nitrogen as the main constituent element,in which a concentration of the nitrogen is from 0.3 to 14 atm %.

[0016] Further, the foregoing first object can be attained by asemiconductor device according to this invention comprising a substratein which semiconductor elements are formed, metal wiring forinterconnecting the semiconductor elements, a dry etching stopper layerand an insulative diffusion barrier layer for covering at least aportion of the metal wiring and at least a portion of the dry etchingstopper layer, in which the dry etching stopper layer has an opening,the opening is filled with part of the metal wiring, at least a portionof the surface on the periphery of the wiring has a region made of amaterial comprising copper as the main ingredient, a portion of theregion made of the material comprising copper as the main ingredient isin contact with the insulative barrier diffusion layer, and the dryetching rate of the dry etching stopper layer is made one-half or lessof that of the dry etching layer of the insulative diffusion barrierlayer.

[0017] Further, the foregoing first object can be attained by asemiconductor device according to this invention comprising a substratein which semiconductor elements are formed, first metal wiring forinterconnecting the semiconductor elements, an insulative diffusionbarrier layer for covering at least the upper surface of the first metalwiring, a first insulative film for covering the insulative diffusionbarrier layer, an intermediate stopper film for covering the firstinsulative film, a second insulative film for covering the intermediatestopper film, a protection insulative film for covering the secondinsulative film, and second metal wiring filled in openings provided inthe insulative diffusion barrier layer, the first insulative film, theintermediate stopper film, the second insulative film and the protectioninsulative film to ensure electric connection to the first metal wiring,in which at least a portion of the surface on the periphery of the firstmetal wiring has a region made of a material comprising copper as themain ingredient, a portion of the region made of the material comprisingcopper as the main ingredient is in contact with the insulativediffusion barrier layer, and the dry etching rate of the intermediatestopper film is one-half or less of that of the insulative diffusionbarrier layer.

[0018] Further, the foregoing second object is attained by a method ofmanufacturing a semiconductor device according this invention comprisingthe steps of: forming, on a substrate in which semiconductor elementsare formed, metal wiring having a region at least a portion of theperipheral surface thereof made of a material comprising copper as amain ingredient; and forming, to cover a region of the metal wiring madeof the material comprising copper as the main ingredient, an insulativediffusion barrier layer having characteristics that a specificdielectric constant is 5 or less, a leak current of the insulativediffusion barrier layer at a test temperature of 140° C., under anelectric field strength of 2 MV/cm is 10 nA or less per 1 cm², and thedielectric breakdown lifetime of the insulative diffusion barrier layerwhen copper is used as an anode at a temperature of 140° C. is at least100 years.

[0019] Further, the foregoing second object is attained by a method ofmanufacturing a semiconductor device according this invention whichcomprises the steps of: forming, on a substrate in which semiconductorelements are formed, metal wiring having a region at least a portion ofthe peripheral surface thereof made of a material comprising copper as amain ingredient; and forming, to cover a region of the metal wiring madeof the material comprising copper as the main ingredient, an insulativediffusion barrier layer using a gas mixture at least containing analkoxy silane represented by the general formula (RO)_(n)SiH_(4−n)(where n is an integer in a range from 1 to 3 and R represents an alkylgroup, an aryl group or a derivative thereof) and an oxidative gas by aplasma CVD method.

[0020] The specific dielectric constant of the insulative diffusionbarrier layer is preferably 1 or more. Since most of insulativematerials generally have the specific dielectric constant of 2 or more,it is preferred to use those having 2 to 5 specific dielectric constant.Further, a leak current at the test temperature and under the electricfield strength described above is as small as possible. Since most ofusual materials have a leak current of 0.01 nA or more per 1 cm², it ispreferred to use those having the leak current from 0.01 to 10 nA.

[0021] Further, the foregoing second object can be attained by a methodof manufacturing a semiconductor device according this invention whichcomprises the step of; forming, on a substrate in which semiconductorelements are formed, metal wiring having a region at least a portion ofthe peripheral surface of which is made of a material comprising copperas a main ingredient; and forming, to cover a region of the metal wiringmade of the material comprising copper as the main ingredient, aninsulative diffusion barrier layer by using an inorganic silane gas oran organic silane gas and, a nitrogen oxide gas or a gas mixturecontaining an oxygen atom-containing gas and a nitrogen atom-containinggas by a plasma CVD method, the insulative diffusion barrier layercomprising oxygen, silicon and nitrogen as main constituent elements inwhich a concentration of the nitrogen is from 0.3 to 14 atm %.

[0022] Further, the foregoing second object is attained by the method ofmanufacturing a semiconductor device according to this invention whichcomprises the step of: forming, on a substrate in which semiconductorelements formed, an insulative etching stopper layer having an opening;forming, to fill the opening provided in the insulative etching stopperlayer, metal wiring having a region at least the upper surface thereofmade of a material comprising copper as a main ingredient; and formingan insulative diffusion barrier layer for covering the region of themetal wiring made of the material comprising copper as the mainingredient and the insulative etching stopper layer, in which the dryetching rate of the insulative etching stopper layer is one-half or lessof that of the insulative diffusion barrier layer.

[0023] Further, the foregoing second object is attained by a method ofmanufacturing a semiconductor device according to this invention whichat least comprises the steps of; forming, on a substrate in whichsemiconductor elements are formed; first metal wiring having a region atleast a portion of the upper surface thereof made of a materialcomprising copper as the main ingredient; forming an insulativediffusion barrier layer to cover the region of the first metal wiringmade of the material comprising copper as the main ingredient; forming afirst insulative film, an intermediate stopper film, a second insulativefilm, a protection insulation film and an etching mask successively tocover the insulative diffusion barrier layer; making a first opening ina portion of the etching mask; making a second opening in a portion ofthe protection insulative film exposed at the bottom of the firstopening; forming a third opening in the second insulative film throughthe second opening; removing the intermediate stopper layer exposed tothe bottom of the third opening to make a fourth opening; and,simultaneously, removing the protection insulative film exposed to thebottom of the first opening; removing the second insulative film belowthe first opening formed in the etching mask; and, simultaneously,removing the first insulative film below the fourth opening; removingthe insulative diffusion barrier layer exposed below the fourth openingto make an opening in the first metal wiring, in which the dry etchingrate for the intermediate stopper film is one-half or less of that ofthe insulative diffusion barrier layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 1 of this invention.

[0025]FIG. 2 is a diagram illustrating the electric field strengthdependence of dielectric breakdown lifetime at a portion betweenadjacent copper wiring.

[0026]FIG. 3 is a diagram illustrating a relative value of the parasiticcapacitance of copper wiring.

[0027]FIG. 4 is a table showing the relation between materials appliedto the insulative diffusion barrier layer and characteristics of thesemiconductor devices formed.

[0028]FIG. 5 is a table showing characteristics for each of P-TMS,P-SiN, BLOk film and P-TEOS.

[0029]FIG. 6 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 2 of this invention.

[0030]FIG. 7 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 3 of this invention.

[0031]FIG. 8 is a diagram showing the relation between the dielectricbreakdown life under the electric fields intensity of 2 MV/cm determinedfrom the electric field dependence of dielectric breakdown life at aportion between adjacent copper wiring, and the silane flow rate uponP-MSO deposition.

[0032]FIG. 9 is a diagram illustrating the relation between thedielectric breakdown life under the electric fields intensity of 2 MV/cmdetermined from the electric field dependence of the dielectricbreakdown life between adjacent copper wiring, and plasma power uponP-MSO deposition.

[0033]FIG. 10 is a diagram showing the electric field intensitydependence of the leak current density in a P-MSO film formed on ann-type silicon substrate.

[0034]FIG. 11 is a diagram illustrating a relation between thedielectric breakdown life under the electric field intensity of 2 MV/cmdetermined from the electric field dependence of the dielectricbreakdown life between adjacent copper wiring and the nitrogenconcentration contained in P-MSO and P-TMS.

[0035]FIG. 12 is a diagram showing the relation between the dielectricbreakdown lifetime under the electric field strength of 2 MV/cmdetermined from the electric field dependence of the dielectricbreakdown lifetime at a portion between adjacent copper wiring and thenitrogen concentration contained in P-MSO and P-TMS.

[0036]FIG. 13 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 4 of this invention.

[0037]FIG. 14 is a schematic cross sectional view for a main portion ofmanufacturing steps for a semiconductor device as Example 4 according tothis invention.

[0038]FIG. 15 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 5 of this invention.

[0039]FIG. 16 is a schematic cross sectional view illustrating a mainportion of steps of manufacturing a semiconductor device according toExample 5 of this invention.

[0040]FIG. 17 is a schematic cross sectional view illustrating a mainportion of the steps of manufacturing a semiconductor device accordingto Example 5 of this invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0041] This invention is to be described by way of examples withreference to the drawings. Each of the drawings is depictedschematically with portions unnecessary for explanation being omitted.

EXAMPLE 1

[0042]FIG. 1 is a cross sectional view showing steps of manufacturing asemiconductor device according to this invention. A description is to bemade successively. After forming a first insulative film 200 comprisingsilicon oxide of 400 nm in thickness on a substrate 100 in whichsemiconductor elements are formed, an opening was provided at a desiredregion of the first insulative film 200 in order to establish electricalconnection with the substrate 100, and a tungsten plug was filledtherein by a CVD method. Then, after coating and baking an SiLK (tradename of products manufactured by The Dow Chemical Company) which is anorganic low dielectric constant insulative film to 325 nm in thicknessto form a second insulative film 201, a first protection insulative film202 comprising silicon oxide of 25 nm in thickness was formed by aplasma CVD method. Then, an opening 400 was provided at a desired regionof the second insulative film 201 and the first protection insulativefilm 202 by a combination of a usual photolithographic method and a dryetching method (FIG. 1(a)). After successively forming a titaniumnitride film of 30 nm in thickness by using a sputtering method and acopper film of 500 nm in thickness by a combination of a sputteringmethod and an electrolytic plating method so as to fill the opening, thetitanium nitride film and the copper film on the first protectioninsulative film 202 were removed by a CMP (Chemical MechanicalPolishing) method, and copper wiring comprising a first conductivebarrier layer 300 made of titanium nitride and a first conductor 301made of copper were formed so as to fill the opening 400 (FIG. 1(b)).

[0043] A first insulative diffusion barrier layer 203 of 50 nm inthickness using a gas mixture as the starting material containingtrimethoxysilane ((CH₃O)₃SiH) as an alkoxy silane and N₂O as anoxidative gas was formed on the copper wiring, by using a parallel platetype plasma CVD method by a double frequency excitation system (13.56MHz on an electrode side and 380 KHz on a wafer side) disclosed in thecatalog for plasma CVD apparatus published from Canon Sales Co., Inc.(Catalog No. 1199SZ1).

[0044] Subsequently, the film formed by using trimethoxysilane as thestarting material gas is simply referred to as P-TMS. Alkoxy silanes andoxidative gases suitable to be used for the method are described inJapanese Patent Laid-Open No. Hei 7-211712. An example of alkoxy silaneis represented by the general formula (RO)_(n)SiH_(4−n) (n=1 to 3), inwhich R in the general formula represents an alkyl group, an aryl groupor a derivative thereof. Alkyl groups having carbon atoms of 1 to 3 arepreferred. Specific example of the alkoxy silane suitably includetrimethoxysilane and triethoxysilane ((C₂H₅)₃SiH). Further, preferableexamples of the oxidative gas include O₂, NO, N₂O, NO₂, CO, CO₂ and H₂O.Hereinafter, after coating and baking SiLK as an organic dielectricconstant insulative film of 325 nm in thickness to form a thirdinsulative film 204 on the first insulative diffusion barrier layer 203comprising the P-TMS, a second protection insulative film 205 comprisingsilicon oxide of 25 nm in thickness was formed by a plasma CVD method toconstitute a semiconductor device (FIG. 1(c)).

[0045] In addition to the structure shown in Example 1, a structure ofusing a silicon nitride film (hereinafter simply referred to as P-SiN)as a first insulative diffusion barrier layer instead of P-TMS, whichP-SiN is formed by a plasma CVD method using silane (SiH₄) and ammonia(NH₃) as the starting material gas, a structure of using a BLOk film,and a structure of using a silicon oxide film (hereinafter simplyreferred to as P-TEOS) formed by a plasma CVD method usingtetraethoxysilane ((C₂H₅)₄Si) and O₂ as the starting material gas wereprovided. The thickness of each of the first insulative diffusionbarrier layers is 50 nm.

[0046] The performance and reliability of the semiconductor deviceshaving copper wiring thus formed were examined. FIG. 2 is a graphshowing the relation between the dielectric breakdown lifetime of theinsulative films at a portion between adjacent copper wiring in thesemiconductor devices thus formed and the electric field strength of theinsulative films under extrapolation as far as the dielectric fieldstrength of 2 MV/cm or less. Since the electric field strength appliedto the adjacent inter-wiring dielectric film is 2 MV/cm when a voltageof 20 V is applied between adjacent wiring at a distance of adjacentcopper wiring of 0.1 μm, it is necessary that the life is 10 years ormore under the electric field strength. The power source voltage in theusual LSI is mostly 5 V or less but the LSI is often used whilegenerating higher voltage in the inside depending on the applicationuse, so that the life under 2 MV/cm is desirably 100 years or more inorder to improve the durability to accidental failure and improve thereliability and the yield of products (a region shown by hatched line inFIG. 2). As shown in FIG. 2, what can maintain the reliability of 100years under the electric field strength of 2 MV/cm was a specimen usingP-TMS as the insulative diffusion barrier layer.

[0047] Further, using the specimen, when the parasitic capacitancebetween the adjacent copper wiring was measured by the use of acapacitance-voltage method (CV method), results as shown in FIG. 3 wereobtained. The parasitic capacitance value when P-TMS is used as theinsulative diffusion barrier layer is expressed as 100%. As can be seenfrom FIG. 3, the parasitic capacitance is minimized in a case of usingP-TMS as the insulative diffusion barrier layer. The parasiticcapacitance was largest in a case of using P-SiN as the insulativediffusion barrier layer which was higher by about 10% compared with thecase of P-TMS. That is, in a case of using P-SiN as the insulativediffusion barrier layer, it is possible that the speed of signalspropagating in the wiring is lowered by about 10%, to deteriorate theLSI performance, compared with a case of using P-TMS, BLOk or P-TEOS.Further, when the leak current between adjacent copper wiring wasmeasured by using the specimen; it was found that the leak currentbetween the adjacent wiring was increased by about 50% in a case ofusing the BLOk film as the insulative diffusion barrier which maypossibly results in erasing of stored information from the capacitanceelement or an increase in the LSI consumption power compared with a caseof using P-TMS, P-SiN or P-TEOS.

[0048]FIG. 4 collectively shows the results described above in which therelations among the materials applied to the first insulative diffusionbarrier layer 203 shown in FIG. 1 and the characteristics ofsemiconductor devices formed are compared with one another. As apparentfrom FIG. 4, a semiconductor device having long time reliability andhigh performance can be attained only when P-TMS is used as theinsulative diffusion barrier layer.

[0049] The following evaluation was performed to demonstrate the reasonthat the semiconductor device of high performance and high reliabilitywas obtained only in the case of using P-TMS as the insulative diffusionbarrier layer as described above.

[0050] A phosphorus-doped n-silicon substrate (substrate resistivity:0.02 Ωcm) was provided on which P-TMS of 200 nm in thickness was formedand, a circular copper electrode of 1 mm in diameter and 300 nm inthickness was formed thereon using a vacuum vapor deposition apparatusand a vapor deposition mask to form a specimen. Instead of P-TMSspecimen of the structure described above, a specimen formed with P-SiNof 200 nm in thickness, a specimen formed with BLOk of 200 nm inthickness and a specimen formed with P-TEOS of 200 nm in thickness werealso provided and four kinds of specimens in total were formed.Specimens in which the insulative film and the circular copper electrodewere formed on the n-silicon substrate as described above (hereinaftersimply referred to as a planar capacitor specimen) were heated to 140°C., and leak current flowing through four kinds of insulative films wasmeasured while grounding the n-silicon substrate and applying a positivevoltage to the copper electrode, and the time till each of theinsulation films caused dielectric breakdown was measured. Further,using the specimens, the specific dielectric constant of each of theinsulative films was measured by a CV method. FIG. 5 collectively showsthe characteristics of each of the insulative films measured asdescribed above. As apparent from FIG. 5, it can be seen that only P-TMSprovides an insulative film having characteristics such as, highperformance of preventing copper diffusion, a low specific dielectricconstant, and a small leak current.

[0051] That is, in accordance with the example of this invention, asemiconductor device having copper wiring with high reliability of ainsulative film between adjacent copper wiring, low parasiticcapacitance between adjacent wiring and with less leak current adjacentwiring can be formed by forming, as the insulative diffusion barrierlayer just above the copper wiring, the insulative film having aspecific dielectric constant of 5 or less, a leak current at 140° C. andunder 2 MV/cm of 10 nA or less per 1 cm², and a dielectric breakdownlife of 100 years or more at 140° C. when using copper as an anode.

[0052] In this example, while trimethoxysilane was used as a reactiongas to form the first insulative diffusion barrier layer, there is noparticular restriction to the gas and use of other alkoxy silane typegases, for example, triethoxysilane can provide a similar effect.Further, similar effect can also be obtained by using an alkoxy silanein which R is an aryl group in the general formula described above.

[0053] Further, while N₂O was used as the oxidative gas to form thefirst insulative diffusion barrier layer in this example, there is noparticular restriction to this gas but a similar effect can be obtainedalso by the use of a gas containing oxygen atom such as O₂, NO₂, NO₂,CO, CO₂ and H₂O. However, use of a gas with high reactivity to coppersuch as O₂ or H₂O is not preferred since the upper surface of copperwiring is oxidized upon plasma CVD to possibly lower the adhesion or anincrease in the wiring resistance.

[0054] Further, while the thickness of P-TMS as the first insulativediffusion barrier layer was 50 nm in this example, the thickness of thefirst insulative diffusion barrier layer may be increased or decreasedin accordance with the reliability or parasitic capacitance of thewiring. However, when the thickness of the insulative diffusion barrierlayer is reduced, for example, to less than 10 nm, the reliability maypossibly be lowered due to the local breakage of a barrier property. Onthe other hand, in a case where the thickness of the first insulativediffusion barrier layer is increased, for example, in excess of 200 nm,since the specific dielectric constant of the first insulative diffusionbarrier layer is generally higher than that of the organic lowdielectric constant insulative film used as the second insulative film201 or the third insulative film 204, it is possible to increase theparasitic capacitance of the wiring. Accordingly, the thickness ispreferably in a range from 10 nm to 200 nm and, more preferably, in arange from 30 nm to 100 nm.

[0055] Further, in this example, while the second insulative film wasformed directly on the first insulative diffusion barrier layer, thisinvention is not restricted to this example but it is possible tooptionally interpose, for example, a dry etching stopper layer betweenthe first insulative diffusion barrier layer and the second insulativefilm.

[0056] Further, in this example, while SiLK which is an organic lowdielectric constant insulative film is used as the second insulativefilm or the third insulative film, the effect of this invention is notprovided only by the combination. Similar effects can be expected alsoby the combination with an organic film containing fluoro resintypically represented by Teflon (trade name of products manufactured byDuPont) or FLARE (trade name of products manufactured by Allied Signal,Inc.), a CVD insulation film using methyltriethoxysilane ((C₂H₅O)₃SiCH₃)as the starting gas, an organic containing silicon oxide filmcontaining, for example, Black Diamond (trade name of productsmanufactured by Applied Materials Co.) or HSG-R7 (trade name of productsmanufactured by Hitachi Chemical Co., Ltd.), a porous insulation filmcontaining, for example, Nanoglass (trade name of products manufacturedby Allied Signal Inc.) or XLK (trade name of products manufactured byAllied Signal Inc.), and an inorganic low dielectric silicon oxide filmwith addition of fluorine, as the low dielectric constant insulativefilm. While this invention is also effective on a case of using a usualsilicon oxide film of not a low dielectric constant insulative film(specific dielectric constant of about 4) as the second insulative filmor the third insulative film, it will be apparent that the combinationwith the low dielectric constant insulative film is most effective inreducing the parasitic capacitance.

[0057] Further, in this example, although the sputtering method andplating method were combined as the copper deposition method, this isnot restrictive but the film can be deposited also by a CVD method orthe like.

[0058] Further, in this example, although the copper wiring layer isformed by only one layer, it is possible to optionally stack the wiringlayers successively. This invention is applicable also to a case offilling the via hole with copper in a method of successively forminglayers having the via hole for electrically inter-connecting the wiringlayers (the so-called single damascene method). Further, this inventionis also applicable to a method of collectively forming layers having thevia hole for electrically interconnecting wiring layers (the so-calleddual damascene method).

EXAMPLE 2

[0059]FIG. 6 is a cross sectional view showing the steps ofmanufacturing of a semiconductor device according to this invention. Thesteps are to be described successively below. After forming a firstinsulative film 200 comprising silicon oxide of 400 nm in thickness on asubstrate 100 in which semiconductor elements are formed, an opening ismade at a desired region of the first insulative film 200 to establishelectrical connection with the substrate 100, and a tungsten plug 500 isfilled by a CVD method. Then, a second conductive barrier layer 302comprising a titanium nitride film of 25 nm in thickness, a secondconductor 303 comprising a copper film of 300 nm in thickness, and athird conductive barrier layer 304 comprising a titanium nitride film of25 nm in thickness were formed by using a sputtering method. Then,copper wiring comprising a second conductive barrier layer 302, a secondconductor 303 and a third conductive barrier layer 304 are formed onlyat a desired region by using a usual photolithographic method and a dryetching method using a chlorine gas (FIG. 6(a)).

[0060] Then, to cover the copper wiring comprising the second conductivebarrier layer 302, the second conductor 303 and the third conductivebarrier layer 304, P-TMS of 50 nm in thickness was formed as a secondinsulative diffusion barrier layer 206 using the same method asdescribed in Example 1 and using a gas mixture containingtrimethoxysilane and N₂O as the starting gas (FIG. 6(b)). Then, aftercoating and baking SiLK (trade name) which is an organic low dielectricconstant insulative film of 325 nm in thickness to form a fourthinsulative film 207, a third protection insulative film 208 comprisingsilicon oxide of 25 nm in thickness was formed by a plasma CVD method(FIG. 6(c)).

[0061] In addition to the structure shown in Example 2, structures usingP-SiN, BLOk and P-TEOS instead of P-TMS as the second insulativediffusion barrier layer 206 were provided. The thickness of each of thesecond insulative diffusion barrier layers is 50 nm.

[0062] When the performance and the reliability of semiconductor deviceshaving the copper wiring formed as described above were examined,semiconductor devices having long time reliability and high performancecould be attained only in the case of using P-TMS as the secondinsulative diffusion barrier layer like that shown in Example 1.

[0063] That is, in accordance with the example of this invention, asemiconductor device having copper wiring with high reliability of theinsulative film between adjacent copper wiring, low parasiticcapacitance between adjacent wiring and with less leak current inadjacent wiring can be formed by forming, as the insulative diffusionbarrier layer just above the copper wiring, an insulative film having aspecific dielectric constant of 5 or less, a leak current at 140° C. andunder 2 MV/cm of 10 nA or less per 1 cm², and a dielectric breakdownlifetime of 100 years or more at 140° C. when using copper as an anode.

[0064] In this example, while trimethoxysilane was used as a reactiongas when the second insulative diffusion barrier layer was formed, thereis no particular restriction to the gas and use of other alkoxy silanetype gases can provide a similar effect.

[0065] Further, while N₂O was used as the oxidative gas when the secondinsulative diffusion barrier layer was formed in this example, there isno particular restriction to the gas but a similar effect can beobtained also with a gas containing oxygen atom such as O₂, NO, NO₂, CO,CO₂ and H₂O. However, use of a gas with high reactivity to copper suchas O₂ or H₂O is not preferred since the upper surface of copper wiringis oxidized upon plasma CVD to possibly lower the adhesion or increasethe wiring resistance.

[0066] Further, while the thickness of P-TMS as the second insulativediffusion barrier layer was 50 nm in this example, the thickness of thefirst insulative diffusion barrier layer may be increased or decreasedin accordance with the reliability or the parasitic capacitance of thewiring. However, when the thickness of the insulative diffusion barrierlayer is reduced, for example, to less than 10 nm, the reliability maypossibly be lowered due to the local breakage of the barrier property.On the other hand, in a case where the thickness of the secondinsulative diffusion barrier layer is increased, for example, in excessof 200 nm, since the specific dielectric constant of the secondinsulative diffusion barrier layer is generally higher than that of theorganic low dielectric constant insulative film used as the fourthinsulative film 207, it may possibly increase the parasitic capacitanceof the wiring. Accordingly, the thickness is preferably in the rangedescribed in Example 1.

[0067] Further, in this example, while SiLK which is the organic lowdielectric constant insulative film is used as the fourth insulativefilm or the third insulative film, the effect of this invention is notprovided only by the combination. Similar effects can be expected alsoby the combination with an organic film containing fluoro resintypically represented by Teflon (trade name of products manufactured byDuPont) or FLARE (trade name of products manufactured by Allied Signal,Inc.), a CVD insulation film using methyltriethoxysilane as the startinggas, an organic containing silicon oxide film containing, for example,Black diamond (trade name of products manufactured by Applied MaterialsCo.) or HSG-R7 (trade name of products manufactured by Hitachi ChemicalCo., Ltd.), a porous insulation film containing, for example, Nanoglass(trade name of products manufactured by Allied Signal Inc.) or XLK(trade name of products manufactured by Allied Signal Inc.), and aninorganic low dielectric silicon oxide film with addition of fluorine,as the low dielectric constant insulative film. While this invention isalso effective on a case of using a usual silicon oxide film of not alow dielectric constant insulative film (specific dielectric constant ofabout 4) as the second insulative film or the third insulative film, itwill be apparent that the combination with the low dielectric constantinsulative film is most effective in reducing the parasitic capacitance.

[0068] Further, in this example, the sputtering method was combined asthe copper deposition method, this is not restrictive but film can bedeposited also by a CVD method or the like.

[0069] Further, in this example, although the copper wiring layer isformed by only one layer, it is possible to optionally stack the wiringlayers successively.

EXAMPLE 3

[0070]FIG. 7 is a cross sectional view showing the steps ofmanufacturing a semiconductor device according to this invention. Thesteps are to be described successively below. After forming a firstinsulative film 200 comprising silicon oxide of 400 nm in thickness on asubstrate 100 in which semiconductor elements are formed, an opening isprovide at a desired region of the first insulative film 200 toestablish electrical connection with the substrate 100, and a tungstenplug 500 is filled by a CVD method. Then, after coating and baking anSiLK (trade name of products manufactured by Dow Chemical Company) whichis the organic low dielectric constant insulative film to 325 nm inthickness to form a second insulative film 201, a first protectioninsulative film 202 comprising silicon oxide of 25 nm in thickness wasformed by a plasma CVD method. Then, an opening 400 is provided at adesired region of the second insulative film 201 and the firstprotection insulative film 202 by combination of usual photolithographicmethod and dry etching method (FIG. 7(a)).

[0071] After forming a titanium nitride film of 30 nm in thickness byusing a sputtering method and a copper film of 500 nm in thickness bycombination of a sputtering method and an electrolytic plating method soas to fill the opening, the titanium nitride film and the copper film onthe first protection insulative film 202 were removed by a CMP (ChemicalMechanical Polishing) method, and copper wiring comprising a firstconductive barrier layer 300 made of titanium nitride and a firstconductor 301 made of copper were formed so as to fill the opening 400(FIG. 7(b)).

[0072] On the copper wire, a third insulative diffusion barrier layer209 of 50 nm in thickness was formed from a gas mixture comprisingsilane (SiH₄) and N₂O as an oxidative gas as the starting material gasby using a parallel plate type plasma CVD method. The plasma power was40 W, the silane flow rate was 50 cc/min, the N₂O flow rate was 2000cc/min and substrate temperature was 350° C. Hereinafter, the filmformed by using silane and N₂O as the starting gas is simply referred toas P-MSO.

[0073] Then, after coating and baking SiLK which is the organic lowdielectric constant insulative film of 325 thickness to form a thirdinsulative film 204 on the third insulative diffusion barrier layer 209comprising P-MSO, a second protection insulative film 205 comprisingsilicon oxide of 25 nm in thickness was formed by a plasma CVD method toconstitute a semiconductor device (FIG. 7(c)).

[0074] In the structure shown in Example 3, several kinds of specimenswere prepared while varying the plasma power, silane flow rate and N₂Oflow rate. Further, a specimen using P-TMS instead of P-MSO as the thirdinsulative diffusion barrier layer was also provided. In this case,several kinds of specimens were provided varying the plasma power,trimethoxysilane flow rate and N₂O flow rate when forming P-TMS as thethird insulative diffusion barrier layer. Further, a structure of usingP-SiN and a structure of using a BLOk film instead of P-MSO and P-TMS asthe third insulative diffusion barrier layer were provided. Thethickness of each of the third insulative diffusion barrier layers is 50nm.

[0075] The performance of the semiconductor devices having copper wiringthus formed were examined. When parasitic capacitance between adjacentcopper wiring formed in each of the semiconductor devices was measuredby a capacitance-voltage method (CV method) by using the same method asshown in Example 1, the parasitic capacitance in a case of using P-MSOas the insulative diffusion barrier layer was substantially equal withthe parasitic capacitance in the case of using P-TMS in Example 1 (FIG.3). That is, since the parasitic capacitance can be decreased by about10% compared with the case of using P-SiN as the insulative diffusionbarrier layer, the speed of signals propagating in the wiring can beimproved by about 10%. Further, when leak current between adjacentcopper wiring was measured by using the specimen, it was found that theleak current between the adjacent wiring was increased by about 50% in acase of using the BLOk film as the insulative diffusion barrier layercompared with a case of using P-MSO, P-TMS or P-SiN, and it may possiblyresult in erasing of stored information from the capacitance element andan increase in the LSI consumption power.

[0076] Then, the reliability of semiconductor devices having copperwiring described above was examined and the result is to be explainedmainly in the case of using P-MSO. FIG. 8 is an example thereof. In FIG.8, the abscissa represents a silane flow rate when P-MSO is deposited asthe third insulative diffusion barrier layer, while the ordinaterepresents the dielectric breakdown lifetime under the electric fieldstrength of 2 MV/cm calculated from the electric field dependence of thedielectric breakdown life between adjacent copper wiring. A N₂O flowrate is 1000 cc/min and plasma power is 30 W upon P-MSO deposition. Asapparent from FIG. 8, by setting the silane flow rate as 30 cc/min and50 cc/min upon deposition of P-MSO, it has been found that necessary andsufficient reliability can be obtained which are superior to the case ofusing BLOk or P-SiN. The same trend, that is, the trend capable ofobtaining necessary reliability when the trimethoxysilane flow rateexceeds a predetermined value was found also in the P-TMS structure.

[0077] Then, FIG. 9 shows a second example illustrating a relationbetween film deposition conditions upon P-MSO deposition and dielectricbreakdown life between adjacent copper wiring. A relation between thedielectric breakdown life between adjacent copper wiring under theelectric field strength of 2 MV/cm and the plasma power was examined bythe same method as illustrated in FIG. 8, while setting the silane flowrate for 50 cc/min in two cases of the N₂O flow rate of 500 cc/min and2000 cc/min. As apparent from FIG. 9, it was found that necessary andsufficient reliability superior to the case of using BLOk or P-SiN couldbe obtained by setting the plasma power from 100 W to 180 W for thesilane flow rate of 50 cc/min and N₂O flow rate of 500 cc/min upon P-MSOdeposition and by setting the plasma power to 30 W to 80 W for thesilane flow rate of 50 cc/min and N₂O flow rate of 2000 cc/min. In thesame manner, similar plasma power dependence was also observed in P-TMSspecimen.

[0078] Then, the leak current and the specific dielectric constant ofthe P-MSO film formed by using film deposition conditions by which thenecessary and sufficient reliability of copper wiring superior to thatusing the BLOk or P-SiN as shown in FIGS. 8 and 9 was obtained weremeasured. FIG. 10 shows an example. After forming P-MSO of 100 nm inthickness on an n-silicon substrate at a silane flow rate of 50 cc/min,a N₂O flow rate of 2000 cc/min and at a plasma power of 40 W, a circularcopper electrode was vapor deposited. Then, FIG. 10 shows a result ofapplying an electric field to P-MSO using the copper electrode as thepositive electrode and measuring the leak current in the P-MSO film witha pico-ampere meter. The leak current under the electric field strengthof 2 MV/cm was about 2 nA (=2×10⁻⁹ A) per 1 cm². Further, the specificdielectric constant of the specimen measured by using the CV method was4.1. Further, when a time leading to dielectric breakdown at 140° C. byapplying an electric field to P-MSO using copper as the positiveelectrode by using the specimen, a result of about 3000 years wasobtained. Only one example is described here for each of the leakcurrent, specific dielectric constant and life to dielectric breakdown,in P-MSO formed by using film deposition conditions capable of obtainingnecessary and sufficient reliability for copper wiring superior to thatusing the BLOk or P-SiN as shown in FIGS. 8 and 9, the leak currentunder 2 MV/cm was in a range from 1 nA to 10 nA per 1 cm², the specificdielectric constant was in a rage from 3.9 to 4.7 and the dielectricbreakdown lifetime was 100 years or more. Similar trends were alsoobserved in a case of using P-TMS although the details thereof wereomitted.

[0079] Then, as a result of a further detailed study on thecharacteristics of P-MSO and P-TMS, it was found that P-MSO and P-TMSformed by using film deposition conditions capable of obtainingnecessary and sufficient reliability of copper wiring superior to thatusing the BLOk or P-SiN have common features. As a result of analysis onthe composition of P-MSO and P-TMS by an XPS (X-ray PhotoelectronSpectroscopy) method and an SIMS (Secondary Ion Mass Spectroscopy)method, it was found that P-MSO and P-TMS contained mainly silicon andoxygen and a minute amount of nitrogen, and a relation exists betweenthe nitrogen concentration contained in the film and the dielectricbreakdown lifetime between adjacent copper wiring extrapolated to 2MV/cm. FIG. 11 is a graph showing an example.

[0080] As apparent from FIG. 11, it can be seen that a semiconductordevice having a dielectric breakdown lifetime of 100 years or more canbe formed in a region of the nitrogen concentration from 0.5 atm % to 12atm % contained in P-MSO and P-TMS.

[0081] Further, as apparent from FIG. 11, it was found that thesemiconductor device having higher reliability than in the case of usingP-SiN film and a block film as the existent material can be formed in aregion of the nitrogen concentration from 0.5 to 12.5 atm % contained inP-MSO and P-TMS.

[0082] Further, for the compound comprising nitrogen, oxygen and siliconon which a Cu barrier property has been studied, the Cu barrier propertywas studied for silicon oxide typically represented, for example, byP-TEOS with the nitrogen concentration of 0%, P-SiN with the nitrogenconcentration of about 57% and SiON with the nitrogen concentration atan intermediate value between them (about 20%). The relation between thedielectric breakdown lifetime and the nitrogen concentration using thematerials described above is as shown in FIG. 12. Since the dielectricbreakdown lifetime tends to be increased as the nitrogen concentrationincreases, it was considered that the Cu barrier property was improvedas the nitrogen concentration in the film was higher in such compoundcomprising nitrogen, oxygen and silicon. However, as shown in FIGS. 11and 12, in the P-MSO and P-TMS comprising silicon, oxygen and nitrogenas the main constituent elements obtained in this invention, it can beseen that there is a range in which a semiconductor device can be formedwhich has a high reliability superior to the expected value in theexistent relation between the dielectric breakdown lifetime and thenitrogen concentration, within a range of the nitrogen concentrationcontained in the film from 0.3 to 14 atm %.

[0083] Further, as shown in FIG. 11, in the use of P-TMS, it includedthose of short dielectric breakdown lifetime while the nitrogenconcentration contained in the film was about 5 atm %. When thecharacteristics of the P-TMS films formed under such conditions wereexamined, the characteristics were deteriorated such that the leakcurrent in the film was about 2 μA (=2×10⁻⁶ A) per 1 cm² and thespecific dielectric constant was about 6. To examine the reason, whenthe P-TMS films deposited under such conditions were subjected to FT-IRanalysis (Fourier Transformation Infrared Spectroscopy), it was foundthat a great amount of carbon was contained in the films. As describedabove, even when the nitrogen concentration contained in the film waswithin an appropriate range as described above, if the film depositioncondition was not appropriate, no desired reliability could sometimes beobtained, for example, because of the increased amount of carbon in thefilms.

[0084] That is, in accordance with the example of this invention, it ispossible to form a semiconductor device having copper wiring with highreliability for the insulative film between adjacent copper wiring, lowparasitic capacitance between adjacent wiring and less leak currentbetween adjacent wiring by forming, as an insulative diffusion barrierlayer just above the copper wiring, an insulative film having adielectric specific constant of 5 or less and a leak current at 140° C.under 2 MV/cm of 10 nA or less per 1 cm² and a dielectric breakdownlifetime of 100 years or more at 140° C. when using copper as an anode,by using silane or trimethoxysilane and N₂O as a starting material gasby using a plasma CVD method.

[0085] Further, in accordance with the example of this invention, it ispossible to form a semiconductor device having copper wiring having adielectric breakdown lifetime under the electric field intensity of 2MV/cm of 100 years or more, low parasitic capacitance between adjacentwiring and less leak current between adjacent currents by forming, as aninsulative diffusion barrier layer just above the copper wiring, asilicon oxide film containing nitrogen from silane or trimethoxysilaneand N₂O as a starting material gas and using plasma CVD method andcontrolling the nitrogen concentration in a range from 0.5 to 12 atm %.

[0086] Further, in accordance with the example of this invention, it ispossible to form a semiconductor device having copper wiring havingreliability superior to a case of using the silicon nitride film and theBLOk film as the existent material, low parasitic capacitance betweenadjacent wiring and less leak current between adjacent wiring byforming, as an insulative diffusion barrier layer just above copperwiring, a silicon oxide film containing nitrogen in which the nitrogenconcentration controlled in a range from 0.5 to 12.5 atm %, by usingsilane or trimethoxysilane and N₂O as a starting material gas by aplasma CVD method.

[0087] Further, in accordance with the example of this invention, it ispossible to form a semiconductor device having copper wiring having aninsulation reliability superior to the prior knowledge, low parasiticcapacitance between adjacent wiring and less leak current betweenadjacent wiring by forming, as an insulative diffusion barrier layerjust above the copper wiring, a silicon oxide film containing nitrogenin which the nitrogen concentration is controlled in a range from 0.3 to14 atm % by using silane or trimethoxysilane and N₂O as a startingmaterial gas and using a plasma CVD method.

[0088] In this example, while silane (SiH₄) was used as the reaction gasupon formation of the third insulative diffusion barrier layer, there isno particular restriction to such gas but similar effects can beobtained also by using other higher silanes represented by the generalformula Si_(n)H_((2n+2)) (n is an integer of 1 or more), for example,disilane (Si₂H₆). Since molecules constituting the gas of higher silaneshave no organic groups, they have a merit of a less possibility ofdeterioration in the reliability such as an increase in leak currentbecause of incorporation of current into the film.

[0089] Further, in this example, trimethoxysilane ((OCH₃)₃SiH) as anorganic silane gas was also used as the reaction gas upon formation ofthe third insulative diffusion barrier layer, there is no particularrestriction on such gas but similar effects can also be obtained byusing other organic silane type gases represented, for example, by thegeneral formulae R_(n)SiH_(4−n), (RO)_(n)SiH_(4−n), R_(m)Si₂H_(6−m), (RO)_(m)Si₂H_(6−m), (RO)_(n)SiR′_(4−n) (where n is an integer of 1 to 4,m is an integer of 1 to 6, R and R′ each represent an alkyl group, arylgroup or derivative thereof). The organic silane type gases are likelyto pose problems that carbon is incorporated into the insulativediffusion barrier layer to deteriorate the insulation characteristics orincrease a specific dielectric constant but they have a merit that thehandleability of the starting gas is easier since the ignition point islow unlike inorganic silane.

[0090] Further, while N₂O was used in this example as the oxidative gasupon formation of the third insulative diffusion barrier layer, there isno particular restriction on such gas but similar effects can beobtained also by other oxide type gases, for example, NO and NO₂.Further, similar effects can be obtained also with a gas mixturecontaining an oxygen atom-containing gas such as O₂, CO, CO₂ and H₂O anda nitrogen atom-containing gas such as N₂ and NH₃, in addition to thesilicon oxide gas described above. Further, it is also possible todeposit films while mixing the noted nitrogen oxide type gas in the gasmixture. However, use of a gas having high reactivity with copper suchas O₂ or H₂O is not preferred since the upper surface of the copperwiring is oxidized upon plasma CVD, to possibly lower the adhesion orincrease the wiring resistance.

[0091] Further, while the parallel plate type plasma excitation systemwas used as the plasma excitation system in this example, the inventionis not restricted only to this system and plasma excitation systemtypically represented by induction coupled plasma excitation system,electron cyclotron resonance plasma excitation system or the like canalso be used in addition to the system described above.

[0092] Further, in this example, while the thickness of P-MSO and P-TMSas the third insulative diffusion barrier layer was 50 nm, the thicknessof the third insulative diffusion barrier layer may be increased ordecreased in accordance with the reliability or parasitic capacitance ofthe wiring. However, when the thickness of the third insulativediffusion barrier layer is reduced, for example, to less than 10 nm, thereliability may possibly be lowered due to the local breakage of abarrier property. On the other hand, in a case where the thickness ofthe first insulative diffusion barrier layer is increased, for example,in excess of 200 nm, since the specific dielectric constant of the thirdinsulative diffusion barrier layer is generally higher than that of theorganic low dielectric constant insulative film used as the secondinsulative film 201 or the third insulative film 204, it is possible toincrease the parasitic capacitance of the wiring. Accordingly, thethickness is preferably in a range from 10 nm to 200 nm and, morepreferably, in a range from 30 nm to 100 nm.

[0093] Further, in this example, while the third insulative film wasformed directly on the second insulative diffusion barrier layer, thisinvention is not restricted to this example but it is possible tooptionally interpose, for example, a dry etching stopper layer betweenthe third insulative diffusion barrier layer and the second insulativefilm.

[0094] Further, in this example, while SiLK which is the organic lowdielectric constant insulative film is used as the second insulativefilm or the third insulative film, the effect of this invention is notprovided only by the combination. Similar effects can be expected alsoby the combination with an organic film containing fluoro resintypically represented by Teflon (trade name of products manufactured byDuPont) or FLARE (trade name of products manufactured by Allied Signal,Inc.), a CVD insulation film using methyltriethoxysilane ((C₂H₅O)₃SiCH₃)as the starting material gas, an organic containing silicon oxide filmcontaining, for example, Black Diamond (trade name of productsmanufactured by Applied Materials Co.) or HSG-R7 (trade name of productsmanufactured by Hitachi Chemical Co., Ltd.), a porous insulation filmcontaining, for example, Nanoglass (trade name of products manufacturedby Allied Signal Co.) or XLK (trade name of products manufactured byAllied Signal Co.), and an inorganic low dielectric silicon oxide filmwith addition of fluorine, as the low dielectric constant insulativefilm. While this invention is effective also to a case of using a usualsilicon oxide film of not a low dielectric constant insulative film(specific dielectric constant of about 4) as the second insulative filmor the third insulative film, it will be apparent that the combinationwith the low dielectric constant insulative film is most effective inreducing the parasitic capacitance.

[0095] Further, in this example, while the sputtering method and theplating method were combined with each other as the copper depositionmethod, this is not restrictive but the film can be deposited also by aCVD method or the like.

[0096] Further, in this example, while the copper wiring layer is formedonly by one layer, it is possible to optionally stack the wiring layerssuccessively. This invention is applicable also to a case of filling avia hole with copper in a method of successively forming layers havingvia holes for electrically inter-connecting the wiring layers (theso-called single damascene method). Further, this invention is alsoapplicable to a method of collectively forming layers having via holesfor electrically inter-connecting wiring layers (so-called dualdamascene method).

EXAMPLE 4

[0097]FIGS. 13 and 14 are cross sectional views showing the steps ofmanufacturing a semiconductor device according to this invention. Thesteps are to be described successively below. After forming a firstinsulative film 200 comprising a silicon oxide of 400 nm in thickness ona substrate 100 in which semiconductor elements were formed, an openingwas provided at a desired region of the first insulative film 200 toestablish electrical connection with the substrate 100, and a tungstenplug 500 was filled by a CVD method. Then, after coating and baking SiLKwhich is an organic low dielectric constant insulative film (trade nameof products manufactured by Dow Chemical Company) of 325 nm in thicknessto form a second insulative film 201, a first etching stopper layer andprotection insulative film 210 comprising silicon carbide as a mainingredient of 25 nm in thickness was formed by a plasma CVD method.Then, an opening 400 was provided at a desired region of the secondinsulative film 201 and the first etching stopper layer and protectioninsulative film 210 by the combination of a usual photolithographicmethod and a dry etching method (FIG. 13(a)).

[0098] After forming a titanium nitride film of 40 nm in thickness byusing a sputtering method and a copper film of 500 nm in thickness bythe combination of a sputtering method and an electrolytic platingmethod successively so as to fill the opening, the titanium nitride filmand the copper film on the first etching stopper layer and protectioninsulative film 210 were removed by a CMP method, and a first copperwiring layer comprising a first conductive barrier layer 300 of titaniumnitride and a first conductor 301 of copper were formed so as to fillthe opening 400. Then, as described in Example 3, a third insulativediffusion barrier layer 209 comprising P-MSO (nitrogen concentration: 3atm %) of 50 nm in thickness was formed using a gas mixture containingsilane and N₂O as the starting material gas by a parallel plate typeplasma CVD system and, after coating and baking SiLK as the organic lowdielectric constant insulative film of 335 nm in thickness on the thirdinsulative diffusion barrier layer 209 comprising P-MSO to form a thirdinsulative film 204, a second etching stopper layer and protectioninsulative film 211 comprising silicon carbide as a main ingredient of25 nm in thickness was formed (FIG. 13(b)).

[0099] Then, a second opening 401 was provided at a desired region ofthe third insulative diffusion barrier layer 209, the third insulativefilm 204 and the second etching stopper layer and protection insulativefilm 211 by the combination of a usual photolithographic method and adry etching method (FIG. 15(c)). A copper wiring interlayer via holecomprising a fourth conductive barrier layer 305 of titanium nitride anda third conductor 306 of copper was formed so as to fill the secondopening 401 by the combination of a sputtering method, an electrolyticmethod and an CMP method to fill the opening (FIG. 14(a)).

[0100] Then, a fourth insulative diffusion barrier layer 212 and a fifthinsulative film 213 and a third etching stopper layer and protectioninsulative film 214, as well as a second copper wiring layer having anopening at a desired region thereof and comprising a fifth conductivebarrier layer 307 of titanium nitride and a fourth conductor 308 ofcopper so as to fill the opening were formed on the via holes byrepeating the steps described above, to constitute a semiconductordevice (FIG. 14(b)).

[0101] In the structure shown in Example 4, while the plasma CVD filmcomprising silicon carbide as the main ingredient of 20 nm in thicknesswas used for the first etching stopper layer and protection insulativefilm 210, the second etching stopper layer and protection insulativelayer 211, several kinds of specimens formed by using each of siliconoxide, silicon nitride, organic group-containing silicon oxide andaluminum oxide were additionally prepared.

[0102] When the performance and the reliability of the thus formedsemiconductor devices were examined, a result was obtained thatvariations in the electric resistance of the second copper wiring layerwas large to lower the conduction yield of the copper wiring interlayervia hole in a case of the specimens using silicon oxide as the first andsecond etching stopper layers and protection insulations, compared witha case of using other materials. To examine the reason, when the crosssection of the second wiring layer and the interlayer via hole wasobserved under an SEM (Secondary Electron Scanning type ElectronMicroscope), it was observed in the specimen using silicon oxide thatwhen the second opening 401 has an opening in a region other than thefirst copper wiring layer, the first etching stopper layer andprotection insulative film 210 just below the opening is dissipated toexpose the second insulative film 201 or engrave the second insulativefilm 201 failing to conduct normal burying of the copper wiringinterlayer via hole. Further, in the region where the second copperwiring layer comprising the fifth conductive barrier layer 307 and thefourth conductor 308 was formed, it was observed such failure that thesecond etching stopper layer and protection insulative layer 211 formedof silicon oxide just below the second copper wiring layer wasdissipated to make the heights of the wiring nonuniform. On thecontrary, such failure was not observed for the specimens usingmaterials other than silicon oxide as the first and second etchingstopper layer and protection insulation films, and also in a case wherethe second opening 401 has an opening in a region other than the copperwiring layer, the first etching stopper layer and protection insulativefilm 210 just below the opening was left substantially as it was.

[0103] To examine the reason why the variations in the wiring resistanceis small and the conduction yield of the via hole is high in thespecimen using silicon oxide as the first and second etching stopperlayer and protection insulation films, the etching rates when therespective materials (silicon oxide, silicon carbide, silicon nitride,organic group-containing silicon oxide and aluminum oxide) were etchedunder the dry etching condition for P-MSO as the third insulativediffusion barrier layer (C₄F₈ gas used) were compared with one another.As a result, it was found that while the etching rate of silicon oxidewas substantially equal to that of P-MSO, the etching rate of othermaterials was low, that is, about ½ to {fraction (1/20)} that of theP-MSO film.

[0104] Then, when the leak current between adjacent copper wiring in thefirst copper wiring layer and the dielectric breakdown life wereevaluated, it provided a result that in any of the specimens thedielectric breakdown lifetime of 100 years or more was obtained at theportion between adjacent copper wiring under the electric fieldintensity of 2 MV/cm, but the leak current between adjacent copperwiring was increased somewhat in a case of using silicon carbide.Further, when the parasitic capacitance of the first copper wiring layerwas measured, it provided a result that the parasitic capacitance wassomewhat increased in a case of using silicon nitride and aluminumoxide. In a case of using organic-containing silicon, although the leakcurrent or parasitic capacitance did not increase, it was observed thata film was peeled occasionally from part of a wafer during the steps offabricating a semiconductor device.

[0105] As described above, while the variations in the wiring resistanceand the conduction yield are improved by the use of materials other thansilicon oxide whose dry etching rate is lower than the P-MSO film, thematerials have their respective features regarding other performances.Therefore, it is desirable that they be used selectively depending onthe application use of the semiconductor device and the feature of theproduction process.

[0106] That is, in accordance with the example of this invention, it ispossible to form a semiconductor device having copper wiring with lessvariations in wiring resistance and a high conduction yield of a viahole in a structure where P-MSO is formed as the insulative diffusionbarrier layer just above the copper wiring, by covering the region justbelow the insulative diffusion barrier layer where copper wiring are notformed with an insulative film having a dry etching rate of ½ or less ofthat of P-MSO.

[0107] While the study has been made in this example on the case ofsilicon carbide, silicon nitride, organic group-containing silicon oxideand aluminum oxide as the etching stopper layer and protectioninsulative film of P-MSO as the insulative diffusion barrier layerformed just above the copper wiring, the effect of the invention is notrestricted only to the combination described above. Similar effects canbe expected so long as the insulative film material has a dry etchingrate of ½ or less of that of P-MSO when the dry etching conditions ofP-MSO are applied thereto. It will be apparent in this case that thespecific dielectric constant and the leak current of the insulative filmare as low as possible.

[0108] Further, in this example, while the thickness of the etchingstopper layer and protection insulative film was 25 nm, the thicknessmay be changed with the view point of the performance of thesemiconductor and the process margin. Since the lowering of thereliability can be suppressed as the thickness of the etching stopperlayer and protection insulative film is larger even when P-MSO as theinsulative diffusion barrier layer is etched excessively, an improvementin product yields can be expected. However, since the specificdielectric constant of the etching stopper layer and protectioninsulative film is usually higher than that of the insulative film usedtherebelow, that is, SiLK with specific dielectric constant of 2.7 inthis example, the parasitic capacitance for the entire wiring maypossibly be increased to lower the performance. On the other hand, whenthe thickness of the etching stopper layer and protection insulativefilm is reduced, an increase in the parasitic capacitance can beminimized but, when P-MSO as the insulative diffusion barrier layer isetched excessively, the insulative film used therebelow, that is, SiLKin this example is exposed to possibly lower the reliability.Accordingly, the thickness of the etching stopper layer and protectioninsulative film is suitably from 15 nm to 150 nm and, more preferably,in a range from 25 nm to 100 nm.

[0109] Further, in this example, while P-MSO containing 3% nitrogenconcentration was formed as the insulative diffusion barrier layer justabove the copper wiring, the nitrogen concentration is not restrictiveand P-MSO with optional nitrogen concentration capable of satisfyingrequired reliability and performance as shown in Example 3 can be used.Further, so long as required reliability and performance can besatisfied, it can be prepared also by using other inorganic silane gasesor organic silane gases instead of silane.

[0110] Further, in this example, while SiLK which is the organic lowdielectric constant insulation film is used as the second, third andfifth insulation films, the effect of the invention is not developedonly by the combination described above. Similar effects can be expectedalso for the combination with an organic film containing fluoro resintypically represented by Teflon (trade name of products manufactured byDuPont) or FLARE (trade name of products manufactured by Allied Signal,Inc.), a CVD insulation film using methyltriethoxysilane ((C₂H₅O)₃SiCH₃)as the starting material gas, an organic containing silicon oxide filmcontaining, for example, Black Diamond (trade name of productsmanufactured by Applied Materials Co.) or HSG-R7 (trade name of productsmanufactured by Hitachi Chemical Co., LTD.), a porous insulation filmcontaining, for example, Nanoglass (trade name of products manufacturedby Allied Signal, Inc.) or XLK (trade name of products manufactured byAllied Signal, Inc.), and an inorganic low dielectric silicon oxide filmwith addition of fluorine, as the low dielectric constant insulativefilm. While this invention is effective also on a case of using a usualsilicon oxide film of not a low dielectric constant insulative film(specific dielectric constant of about 4) as the second, third, or fifthinsulative film, it will be apparent that the combination with the lowdielectric constant insulative film is most effective in reducing theparasitic capacitance.

[0111] Further, in this example, the sputtering method and the platingmethod were combined with each other as the copper deposition method,this is not restrictive but the film can be deposited also by a CVDmethod or the like.

[0112] Further, while the copper wiring layer is formed only with twolayers in this example, it is possible to optionally stack the wiringlayers successively.

EXAMPLE 5

[0113] FIGS. 15 to 17 are cross sectional views illustrating the stepsof manufacturing a semiconductor device having a dual damascene typecopper wiring structure according to this invention. The steps is to bedescribed successively. After forming a first insulative film 200comprising silicon oxide of 400 nm in thickness on a substrate 100 inwhich semiconductor elements were formed, an opening was provided at adesired region in the first insulative film 200 for establishingelectrical connection with the substrate 100, which was filled with atungsten plug 500 by a CVD method. Then, after coating and baking SiLK(trade name of products manufactured by Dow Chemical Company) which isan organic low dielectric constant insulative film of 320 nm inthickness to form a second insulative film 201, a first etching stopperlayer and protection insulative film 210 comprising silicon carbide as amain ingredients of 25 nm in thickness was formed by a plasma CVDmethod. Then, an opening was provided at a desired region of the secondinsulative film 201 and the first etching stopper layer and protectioninsulative film 210 by the combination of usual photo-lithographicmethod and dry etching method and, after forming a titanium nitride filmof 30 nm in thickness by using a sputtering method and a copper film of500 nm in thickness by the combination of a sputtering method and anelectrolytic plating method successively so as to fill the opening, thetitanium nitride film and the copper film on the first etching stopperlayer and protection insulative film 210 were removed by the CMP method,and a first copper wiring layer comprising a first conductive barrierlayer 300 of titanium nitride and a first conductor 301 of copper wasformed so as to fill the opening 400 (FIG. 17(a)).

[0114] Then, as described in Example 3 a third insulative diffusionbarrier layer 209 comprising P-MSO (nitrogen concentration: 3 atm %) of50 nm in thickness, a third insulative film 204 comprising SiLK which isthe organic low dielectric constant insulative film of 325 nm inthickness, a first intermediate stopper film 215 comprising siliconcarbide as a main ingredient of 25 nm film thickness, a sixth insulativefilm 216 comprising SiLK which is the organic low dielectric constantinsulative film of 325 nm in thickness, and a fourth etching stopperlayer and protection insulative film 217 were formed successively byusing a gas mixture containing silane and N₂O as a starting material gasby a parallel plate type plasma CVD system on the copper wiring layer.Then, a first hard mask 218 comprising silicon oxide of 75 nm inthickness was formed, and a third opening 402 was made at a desiredregion of the first photoresist 600 and the first hard mask 218 by thecombination of usual photolithographic method and dry etching method(FIG. 15(b)).

[0115] Then, after removing the first photoresist 600 by a resist asher,and applying a resist so as to cover the opening provided at the firsthard mask 218 by using a photolithographic method again to performexposure and development, thereby making an opening at a desired regionof the second photoresist 601. Subsequently, a fourth opening 403 wasprovided at a desired region of the fourth etching stopper layer andprotection insulative film 217 by using the second photoresist 601 as anetching mask and using a dry etching method (FIG. 16(a)).

[0116] Then, after removing the second photoresist 601 by a resistasher, an opening was provided at the sixth insulative film 216 by usingthe fourth etching stopper layer and protection insulative film 217 asan etching mask. Further, the etching gas was switched to a gas mixtureof CH₄ and oxygen to perform dry etching, and openings were made atfourth etching stopper layer and protection insulation film 217 by usingthe first hard mark 218 as the etching mask and to the firstintermediate stopper films 215 by using the sixth insulative film 216 asthe etching mask (FIG. 16(b)),

[0117] Then, the etching gas was switched again to ammonia and etchingwas conducted for a period of time corresponding to about 420 nm beingconverted into the etched thickness of the SiLK film to make an openingin the sixth insulative film 216 and the third insulative film 204. Inthis case, since the first hard mask 218, the fourth etching stopperlayer and protection insulative film 217, the first intermediate stopperfilm 215 and the third insulative diffusion barrier layer 209 werescarcely etched with the ammonia gas, a structure shown in FIG. 17(a)was obtained.

[0118] Then, to remove the third insulative diffusion barrier layer 209,after dry etching by 75 nm being converted into the thickness of P-MSOusing C₄F₈ series gas, cleaning was performed and a second copper wiringlayer having a via hole comprising a sixth conductive barrier layer 309of titanium nitride of 30 nm in thickness and a fifth conductor 310 ofcopper was formed by a combination of a sputtering method, anelectrolytic method and a CMP method, on which a fifth insulativediffusion barrier layer 219 comprising P-MSO of 50 nm in thickness, aseventh insulative film 220 comprising SiLK of 325 nm in thickness and afourth protection insulative film 221 comprising silicon oxide of 25 nmin thickness were further formed to constitute a semiconductor device(FIG. 17(b)).

[0119] In the structure shown in Example 5, while a plasma CVD filmcomprising silicon carbide as a main ingredient of 25 nm in thicknesswas used as the first intermediate stopper film 215, several kinds ofspecimens prepared by using silicon oxide, silicon nitride, organicgroup-containing silicon oxide and aluminum oxide respectively wereprepared additionally.

[0120] When the performance and the reliability of the thus formedsemiconductor devices were examined, it provided a result that thevariations of electric resistance in the second copper wiring layer andthe connection hole were increased in the specimen using silicon oxideas the first intermediate stopper film compared with a case of usingother materials. When the cross section of the second copper wiringlayer and the interlayer via hole were observed under the SEM to examinethe reason, it was often observed for the specimen using silicon oxidethat the first intermediate stopper film 215 which should be presentjust below the second copper wiring layer was dissipated to make theheights of the wiring nonuniform or the shape of the connection holeundesirable. On the contrary, such failure was not observed for thespecimens using materials other than silicon oxide as the firstintermediate stopper film. When the reason was examined furtherspecifically, it has been found that when the dry etching was performedto make the opening in the third insulative diffusion barrier layer 209comprising P-MSO, the first intermediate film 215 is also etchedsimultaneously to expose the third insulative film comprising SiLK orengrave the film in a case of using silicon oxide as the firstintermediate stopper film. On the other hand, in a case of using siliconcarbide, silicon nitride, organic group-containing silicon oxide oraluminum oxide as the first intermediate stopper layer, since the dryetching rate is lower compared with P-MSO as described also in Example5, the first intermediate stopper film 215 was not dissipated even whenthe opening was made in the third insulative diffusion barrier layer209.

[0121] Then, when the leak current between the adjacent copper wiring inthe second copper wiring layer and the dielectric breakdown lifetimewere evaluated, it provided a result for any of the specimens that thedielectric breakdown lifetime for a portion between adjacent copperwiring was 100 year or more under the electric field intensity of 2MV/cm, but the leak current between the adjacent copper wiring increasedsomewhat in a case of using silicon carbide as the first intermediatestopper film. Further, when the parasitic capacitance of the secondcopper wiring layer was measured, it provided a result that theparasitic capacitance increased somewhat in a case of using siliconnitride and aluminum oxide. In a case of using organic-containingsilicon, while the leak current or parasitic capacitance did notincrease, it was observed that films were peeled occasionally from somewafers during the steps of manufacturing semiconductor devices.

[0122] As has been described above, in the step of manufacturing thesemiconductor devices having the dual damascene type copper wiringstructure as described in this example, the variations of the wiringresistance and the via hole resistance can be improved by using thematerials other than silicon oxide with a lower dry etching ratecompared with the P-MSO film as the first intermediate stopper. However,since the materials has their respective features regarding otherperformances, it is desirable to selectively use them depending on theapplication uses of the semiconductor device and the features of theproduction process.

[0123] That is, in accordance with the example of the invention, it ispossible to form a semiconductor device having copper wiring with lessvariations of the wiring resistance and high reliability in a case offorming P-MSO as the insulative diffusion barrier layer just above thefirst copper wiring and forming a dual damascene type copper wiringhaving a via hole to the first copper wiring, by using an insulativefilm having a dry etching rate of ½ or less of that of P-MSO for thematerial forming the first intermediate stopper as a fabrication maskfor the via hole.

[0124] In this example, while the first intermediate stopper film hasbeen studied taking silicon carbide, silicon nitride, organicgroup-containing silicon oxide and aluminum oxide as examples, theeffects of the invention are not restricted only to the combinationsdescribed above. Similar effects can be expected providing that theinsulative film material has a dry etching rate ½ or less of that ofP-MSO under the application of the dry etching condition for P-MSO. Inthis case, it will be apparent that the specific dielectric constant andthe leak current of the insulative film are desirable as low aspossible.

[0125] Further, in this invention, while the thickness of the firstintermediate stopper film was 25 nm, it is possible to change thethickness with a view point of the semiconductor performance and theprocess margin. Since the lowering of the reliability can be suppressedas the thickness of the first intermediate stopper is larger even whenthe P-MSO as the insulative diffusion barrier layer is etchedexcessively, an improvement in the productive yield can be expected.However, since the specific dielectric constant of the firstintermediate stopper layer is generally higher than the specificdielectric constant of the insulative film used therebelow, that is,SiLK of specific dielectric constant of 2.7 in this example, it ispossible that the parasitic capacitance of the entire wiring mayincrease to lower the performance. On the other hand, while an increasein the parasitic capacitance can be minimized when the thickness of thefirst intermediate stopper film is reduced, when P-MSO as the insulativediffusion barrier layer is etched excessively, the insulative film usedtherebelow, that is, SiLK in this example is exposed to possibly lowerthe reliability. Accordingly, the thickness of the first intermediatestopper film is appropriately from 15 nm to 150 nm and, more preferably,in a range from 25 nm to 100 nm.

[0126] Further, in this example, P-MSO containing 3 atm % of nitrogenconcentration was formed as the insulative diffusion barrier layer justabove the copper wiring, the nitrogen concentration is not restrictivebut P-MSO with any nitrogen concentration capable of satisfying requiredreliability and performance as shown in Example 3 can be used. Further,so long as the required reliability and performance are satisfied, it isalso possible to use films prepared by gases using other inorganicsilane or organic silane gases instead of silane.

[0127] Further, in this example, while SiLK which is the organic lowdielectric insulative film is used as the second, third, sixth andseventh insulative films, the effects of invention are not provided onlywith the combination described above. Similar effects can also beexpected also by the combination with an organic film containing fluororesin typically represented by Teflon (trade name of productsmanufactured by DuPont) or FLARE (trade name of products manufactured byAllied Signal, Inc.), a CVD insulation film using methyltriethoxysilane((C₂H₅O)₃SiCH₃) as the starting material gas, an organic containingsilicon oxide film containing, for example, Black Diamond (trade name ofproducts manufactured by Applied Materials Co.) or HSG-R7 (trade name ofproducts manufactured by Hitachi Chemical, Co., Ltd.), a porousinsulation film containing, for example, Nanoglass (trade name ofproducts manufactured by Allied Signal Inc.) or XLK (trade name ofproducts manufactured by Allied Signal Inc), and an inorganic lowdielectric silicon oxide film with addition of fluorine, as the lowdielectric constant insulative film. While this invention is effectivealso on a case of using a usual silicon oxide film of not a lowdielectric constant insulative film (specific dielectric constant ofabout 4) as the second, third, third, sixth or seventh insulative film,it will be apparent that the combination with the low dielectricconstant insulative film is most effective in reducing the parasiticcapacitance.

[0128] Further, in this example, the sputtering method and the platingmethod were combined as the copper deposition method, this is notrestrictive but the film can be deposited also by a CVD method or thelike.

[0129] Further, in this example, while the copper wiring layer is formedonly with two layers, it is possible to optionally stack the wiringlayers successively.

[0130] This invention can provide a semiconductor device having copperwiring of high performance and high reliability, as well as amanufacturing method therefor.

1. A semiconductor device comprising; a substrate in which semiconductorelements are formed; metal wiring for interconnecting the semiconductorelements; and an insulative diffusion barrier layer for covering atleast a portion of the metal wiring; wherein at least a portion of thesurface on the periphery of the metal wiring has a region made of amaterial comprising copper as a main ingredient, a portion of the regionmade of the material comprising copper as the main ingredient is incontact with the insulative diffusion barrier layer, and the insulativediffusion barrier layer has characteristics that the specific dielectricconstant is 5 or less, a leak current of the insulative diffusionbarrier layer at a test temperature of 140° C., under an electric fieldstrength of 2 MV/cm is 10 nA or less per 1 cm², and the dielectricbreakdown lifetime of the insulative diffusion barrier layer when copperis used as an anode at a temperature of 140° C. is at least 100 years.2. A semiconductor device as defined in claim 1, wherein a region justbelow the insulative diffusion barrier layer comprises the metal wiringand an insulative etching stopper layer, a portion of the metal wiringin contact with the insulative diffusion barrier layer has a region madeof a material comprising copper as a main ingredient, and a dry etchingrate of the insulative etching stopper layer is one-half or less of thatof the insulative diffusion barrier layer.
 3. A semiconductor device asdefined in claim 2, wherein the insulative etching stopper layercomprises an insulative layer selected from silicon carbide, siliconnitride, organic group-containing silicon oxide and aluminum oxide as amain ingredient.
 4. A semiconductor device comprising; a substrate inwhich semiconductor elements are formed; metal wiring forinterconnecting the semiconductor elements; and an insulative diffusionbarrier layer for covering at least a portion of the metal wiring;wherein at least a portion of the surface on the periphery of the metalwiring has a region made of a material comprising copper as a mainingredient, a portion of the region made of a material comprising copperas the main ingredient is in contact with the insulative diffusionbarrier layer, and the insulative diffusion barrier layer is formed byusing a gas mixture containing at least an alkoxy silane represented bythe general formula (RO)_(n)SiH_(4−n) (where n is an integer in a rangefrom 1 to 3 and R represents an alkyl group, an aryl group or aderivative thereof) and an oxidative gas by a plasma CVD method.
 5. Asemiconductor device as defined in claim 4, wherein a region just belowthe insulative diffusion barrier layer comprises the metal wiring and aninsulative etching stopper layer, a portion of the metal wiring incontact with the insulative diffusion barrier layer has a region made ofa material comprising copper as a main ingredient, and a dry etchingrate of the insulative etching stopper layer is one-half or less of thatof the insulative diffusion barrier layer.
 6. A semiconductor device asdefined in claim 5, wherein the insulative etching stopper layercomprises an insulative layer selected from silicon carbide, siliconnitride, organic group-containing silicon oxide and aluminum oxide as amain ingredient.
 7. A semiconductor device comprising: a substrate inwhich semiconductor elements are formed; metal wiring forinterconnecting the semiconductor elements; and an insulative diffusionbarrier layer for covering at least a portion of the metal wiring;wherein at least a portion of the surface on the periphery of the metalwiring has a region made of a material comprising copper as a mainingredient, a portion of the region made of the material comprisingcopper as the main ingredient is in contact with the insulativediffusion barrier layer, and the insulative diffusion barrier layercomprises oxygen, silicon and nitrogen as main constituent elements, aconcentration of the nitrogen being from 0.3 to 14 atm %.
 8. Asemiconductor device as defined in claim 7, wherein a region just belowthe insulative diffusion barrier layer comprises metal wiring and aninsulative etching stopper layer, a portion of the metal wiring incontact with the insulative diffusion barrier layer has a region made ofa material comprising copper as a main ingredient, and a dry etchingrate of the insulative etching stopper layer is one-half or less of thatof the insulative diffusion barrier layer.
 9. A semiconductor device asdefined in claim 8, wherein the insulative etching stopper layercomprises an insulative layer selected from silicon carbide, siliconnitride, organic group-containing silicon oxide and aluminum oxide as amain ingredient.
 10. A semiconductor device comprising; a substrate inwhich semiconductor elements are formed; first metal wiring forinterconnecting the semiconductor elements; an insulative diffusionbarrier layer for covering at least the upper surface of the first metalwiring; a first insulative film for covering the insulative diffusionbarrier layer; an intermediate stopper film for covering the firstinsulative film; a second insulative film for covering the intermediatestopper film; a protection insulative film for covering the secondinsulative film; and second metal wiring filled in openings provided inthe insulative diffusion barrier layer, the first insulative film, theintermediate stopper film, the second insulative film and the protectioninsulative film to ensure electric connection to the first metal wiring;wherein a portion of the first metal wiring in contact with theinsulative diffusion barrier layer has a region made of a materialcomprising copper as a main ingredient, a portion of the region made ofthe material comprising copper as the main ingredient is in contact withthe insulative diffusion barrier layer, and the insulative diffusionbarrier layer has characteristics that a specific dielectric constant is5 or less, a leak current of the insulative diffusion barrier layer at atest temperature of 140° C., under an electric field strength of 2 MV/cmis 10 nA or less per 1 cm², and the dielectric breakdown lifetime of theinsulative diffusion barrier layer when copper is used as an anode at atemperature of 140° C. is at least 100 years.
 11. A semiconductor deviceas defined in claim 10, wherein a dry etching rate of the intermediatestopper layer is one-half or less of that of the insulative diffusionbarrier layer.
 12. A semiconductor device as defined in claim 10,wherein the intermediate stopper film comprises an insulative layerselected from silicon carbide, silicon nitride, organic group-containingsilicon oxide and aluminum oxide as a main ingredient.
 13. Asemiconductor device comprising: a substrate in which semiconductorelements are formed; first metal wiring for interconnecting thesemiconductor elements; an insulative diffusion barrier layer forcovering at least the upper surface of the first metal wiring; a firstinsulative film for covering the insulative diffusion barrier layer; anintermediate stopper film for covering the first insulative film; asecond insulative film for covering the intermediate stopper film; aprotection insulative film for covering the second insulative film; andsecond metal wiring filled in openings provided in the insulativediffusion barrier layer, the first insulative film, the intermediatestopper film, the second insulative film and the protection insulativefilm to ensure electric connection to the first metal wiring; wherein aportion of the first metal wiring in contact with the insulativediffusion barrier layer has a region made of a material comprisingcopper as a main ingredient, a portion of the region made of thematerial comprising copper as the main ingredient is in contact with theinsulative diffusion barrier layer, and the insulative diffusion barrierlayer is formed by using a gas mixture containing at least an alkoxysilane represented by the general formula (RO)_(n)SiH_(4−n) (where n isan integer in a range from 1 to 3 and R represents an alkyl group, anaryl group or a derivative thereof) and an oxidative gas, by a plasmaCVD method.
 14. A semiconductor device as defined in claim 13, wherein adry etching rate of the intermediate stopper layer is one-half or lessof that of the insulative diffusion barrier layer.
 15. A semiconductordevice as defined in claim 13, wherein the intermediate stopper filmcomprises an insulative layer selected from silicon carbide, siliconnitride, organic group-containing silicon oxide and aluminum oxide as amain ingredient.
 16. A semiconductor device comprising: a substrate inwhich semiconductor elements are formed; first metal wiring forinterconnecting the semiconductor elements; an insulative diffusionbarrier layer for covering at least the upper surface of the first metalwiring; a first insulative film for covering the insulative diffusionbarrier layer; an intermediate stopper film for covering the firstinsulative film; a second insulative film for covering the intermediatestopper film; a protection insulative film for covering the secondinsulative film; and second metal wiring filled in openings provided inthe insulative diffusion barrier layer, the first insulative film, theintermediate stopper film, the second insulative film and the protectioninsulative film to ensure electric connection to the first metal wiring;wherein a portion of the first metal wiring in contact with theinsulative diffusion barrier layer has a region made of a materialcomprising copper as a main ingredient, a portion of the region made ofthe material comprising copper as the main ingredient is in contact withthe insulative diffusion barrier layer, and the insulative diffusionbarrier layer comprises oxygen, silicon and nitrogen as main constituentelements and a concentration of the nitrogen is from 0.3 to 14 atm %.17. A semiconductor device as defined in claim 16, wherein a dry etchingrate of the intermediate stopper layer is one-half or less of that ofthe insulative diffusion barrier layer.
 18. A semiconductor device asdefined in claim 16, wherein the intermediate stopper film comprises aninsulative layer selected from silicon carbide, silicon nitride, organicgroup-containing silicon oxide and aluminum oxide as a main ingredient.19. A method of manufacturing a semiconductor device comprising thesteps of: forming, on a substrate in which semiconductor elements areformed, metal wiring having a region at least a portion of theperipheral surface thereof made of a material comprising copper as amain ingredient; and forming, to cover a region of the metal wiring madeof the material comprising copper as the main ingredient, an insulativediffusion barrier layer having characteristics that the specificdielectric constant is 5 or less, the leak current of the insulativediffusion barrier layer at a test temperature of 140° C., under anelectric field strength of 2 MV/cm is 10 nA or less per 1 cm², and thedielectric breakdown lifetime of the insulative diffusion barrier layerwhen copper is used as an anode at a temperature of 140° C. is at least100 years.
 20. A method of manufacturing a semiconductor device asdefined in claim 19, wherein the oxidative gas contains at least onekind of gas selected from the group consisting of NO, N₂O, NO₂, CO andCO₂.
 21. A method of manufacturing a semiconductor device comprising thesteps of: forming, on a substrate in which semiconductor elements areformed, metal wiring having a region at least a portion of theperipheral surface thereof made of a material comprising copper as amain ingredient; and forming, to cover a region of the metal wiring madeof the material comprising copper as the main ingredient, an insulativediffusion barrier layer using a gas mixture at least containing analkoxy silane represented by the general formula (RO)_(n)SiH_(4−n)(where n is an integer in a range from 1 to 3 and R represents an alkylgroup, an aryl group or a derivative thereof) and an oxidative gas, by aplasma CVD method.
 22. A method of manufacturing a semiconductor deviceas defined in claim 21, wherein the oxidative gas contains at least onekind of gas selected from the group consisting of NO, N₂O, NO₂, CO andCO₂.
 23. A method of manufacturing a semiconductor device comprising:forming, on a substrate in which semiconductor elements are formed,metal wiring having a region at least a portion of the peripheralsurface thereof made of a material comprising copper as a mainingredient; and forming, to cover a region of the metal wiring made ofthe material comprising copper as the main ingredient, an insulativediffusion barrier layer comprising oxygen, silicon and nitrogen as mainconstituent elements in which a concentration of the nitrogen is from0.3 to 14 atm % by using an inorganic silane gas or an organic silanegas and, a nitrogen oxide gas or a gas mixture of an oxygenatom-containing gas and a nitrogen atom-containing gas by a plasma CVDmethod.
 24. A method of manufacturing a semiconductor device as definedin claim 23, wherein the inorganic silane gas at least contains one kindof gas selected at least from the group consisting of higher silanesrepresented by the general formula: Si_(n)H_((2n+2)) where n is aninteger of 1 or greater, and the organic silane gas at least containsone kind of gas selected at least from the group of the general formula:R_(n)SiH_(4−n), (RO)_(n)SiH_(4−n), R_(m)Si₂H_(6−m), (RO)_(m)Si₂H_(6−m),(RO)_(n)SiR′_(4−n) in which n is an integer in a range of 1 to 4, m isan integer in a range of 1 to 6, R and R′ each represents an alkylgroup, an aryl group or a derivative thereof.
 25. A method ofmanufacturing a semiconductor device as defined in claim 23, wherein thenitrogen oxide gas at least contains one kind of gas selected at leastfrom the group consisting of N₂O, NO and NO₂, the oxygen atom-containinggas at least contains one kind of gas selected at least from the groupconsisting of O₂, CO, CO₂, H₂O, N₂O, NO and NO₂, and the nitrogenatom-containing gas at least contains one kind of gas selected at leastfrom the group consisting of N₂, NH₃, N₂O, NO and NO₂.
 26. A method ofmanufacturing a semiconductor device as defined in claim 24, wherein thenitrogen oxide gas at least contains one kind of gas selected at leastfrom the group consisting of N₂O, NO and NO₂, the oxygen atom-containinggas at least contains one kind of gas selected at least from the groupconsisting of O₂, CO, CO₂, H₂O, N₂O, NO and NO₂, and the nitrogenatom-containing gas at least contains one kind of gas selected at leastfrom the group consisting of N₂, NH₃, N₂O, NO and NO₂.
 27. A method ofmanufacturing a semiconductor device at least comprising the steps of;forming, on a substrate in which semiconductor elements are formed, aninsulative etching stopper layer having openings; forming metal wiringhaving a region at least a portion of the upper surface thereof made ofa material comprising copper as a main ingredient to fill the openingsprovided in the etching stopper layer; and forming an insulativediffusion barrier layer to cover the region of the metal wiring made ofthe material comprising copper as the main ingredient; wherein a dryetching rate of the insulative etching stopper layer is one-half or lessof that of the insulative diffusion barrier layer.
 28. A method ofmanufacturing a semiconductor device as defined in claim 27, wherein theinsulative etching stopper layer comprises an insulative layer selectedfrom silicon carbide, silicon nitride, organic group-containing siliconoxide and aluminum oxide as a main ingredient.
 29. A method ofmanufacturing a semiconductor device as defined in claim 27, wherein theinsulative diffusion barrier layer has characteristics that a specificdielectric constant is 5 or less, a leak current of the insulativediffusion barrier layer at a test temperature of 140° C., under anelectric field strength of 2 MV/cm is 10 nA or less per 1 cm², and thedielectric breakdown lifetime of the insulative diffusion barrier layerwhen copper is used as an anode at a temperature of 140° C. is at least100 years.
 30. A method of manufacturing a semiconductor device asdefined in claim 27, wherein the insulative diffusion barrier layer isformed by using a gas mixture at least containing an alkoxy silanerepresented by the general formula (RO)_(n)SiH_(4−n) (where n is aninteger in a range from 1 to 3 and R represents an alkyl group, an arylgroup or a derivative thereof) and an oxidative gas by a plasma CVDmethod.
 31. A method of manufacturing a semiconductor device as definedin claim 27, wherein the insulative diffusion barrier layer is formed byusing an inorganic silane gas or an organic silane gas and, a nitrogenoxide gas or a gas mixture containing an oxygen atom-containing gas anda nitrogen atom-containing gas by a plasma CVD method and comprisesoxygen, silicon and nitrogen as main constituent elements in which aconcentration of the nitrogen is from 0.3 to 14 atm %.
 32. A method ofmanufacturing a semiconductor device at least comprising the steps of:forming, on a substrate in which semiconductor elements are formed,first metal wiring having a region at least a portion of the uppersurface thereof made of a material comprising copper as a mainingredient; forming an insulative diffusion barrier layer to cover theregion of the first metal wiring made of the material comprising copperas the main ingredient; forming a first insulative film, an intermediatestopper film, a second insulative film, a protection insulation film andan etching mask successively to cover the insulative diffusion barrierlayer; making a first opening at a portion of the etching mask; making asecond opening at a portion of the protection insulative film exposed tothe bottom of the first opening; making a third opening in the secondinsulative film through the second opening; removing the intermediatestopper layer exposed to the bottom of the third opening to make afourth opening; simultaneously, removing the protection insulative filmexposed to the bottom of the first opening; removing the secondinsulative film below the first opening made in the etching mask;simultaneously, removing the first insulative film below the fourthopening; and removing the insulative diffusion barrier layer exposedbelow the fourth opening to make an opening in the first metal wiring;wherein a dry etching rate of the intermediate stopper film is one-halfor less of that of the insulative diffusion barrier layer.
 33. A methodof manufacturing a semiconductor device as defined in claim 29, whereinthe intermediate stopper layer comprises an insulative layer selectedfrom silicon carbide, silicon nitride, organic group-containing siliconoxide and aluminum oxide as a main ingredient.
 34. A method ofmanufacturing a semiconductor device as defined in claim 29, wherein theinsulative diffusion barrier layer has characteristics that a specificdielectric constant is 5 or less, a leak current of the insulativediffusion barrier layer at a test temperature of 140° C., under anelectric field strength of 2 MV/cm is 10 nA or less per 1 cm², and thedielectric breakdown lifetime of the insulative diffusion barrier layerwhen copper is used as an anode at a temperature of 140° C. is at least100 years.
 35. A method of manufacturing a semiconductor device asdefined in claim 29, wherein the insulative diffusion barrier layer isformed by using a gas mixture at least containing an alkoxy silanerepresented by the general formula (RO)_(n)SiH_(4−n) (where n is aninteger in a range from 1 to 3 and R represents an alkyl group, an arylgroup or a derivative thereof) and an oxidative gas by a plasma CVDmethod.
 36. A method of manufacturing a semiconductor device as definedin claim 29, wherein the insulative diffusion barrier layer is formed byusing a gas mixture containing an inorganic silane gas or an organicsilane gas and, a nitrogen oxide gas or, an oxygen atom-containing gasand a nitrogen atom-containing gas by a plasma CVD method, and comprisesoxygen, silicon and nitrogen as main constituent elements in which aconcentration of the nitrogen is from 0.3 to 14 atm %.